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Semiconductor Test Structure and Design
Research design and algorithms for achieving high quality test and cost-effective improvement of testability for ICs
Reducing test cost
Built-in Self Test(BIST) for reducing test equipment cost
Test compression, ATPG, Memory tests for reducing test data volume and test application time
Improving test quality
Fault modeling, Delay tests
Design for testability(DFT)
Improving yield
Diagnosis
High-speed Testing and Signaling
Research signal integrity(SI) and power integrity(PI) for high-speed testing and high-speed I/O system design
(SI) Analyzing and mitigating various effects that can degrade the quality of electrical signal due to high bit rates
Impedance matching, Reflection, Delay, Crosstalk, Jitter
(PI) Managing power supply of the transistors from variations for maintaining within a specified tolerance value
IR drop, Plane resonance, SSO/SSN
Analyzing interconnections in the chip, package, and PCB(board)
Mid- to Long-term Technology Strategy
Analysis of mid- to long-term emerging technologies and establishment of S&T policies and strategies